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학술지 A 4-GHz All Digital PLL with Low-Power TDC and Phase-Error Compensation
Cited 26 time in scopus Download 5 time Share share facebook twitter linkedin kakaostory
저자
이자열, 박미정, 민병훈, 김성도, 박문양, 유현규
발행일
201208
출처
IEEE Transactions on Circuits and Systems I : Regular Papers, v.59 no.8, pp.1706-1719
ISSN
1549-8328
출판사
IEEE
DOI
https://dx.doi.org/10.1109/TCSI.2012.2206500
협약과제
11MB5600, 2세대/3세대/4세대 이동통신을 지원하는 RFIC/PAM 개발, 유현규
초록
This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed reference clocks does not only reduce a dynamic power in its delay chain, but simplify a fractional phase-error correction. The phase-error compensator is introduced to avoid big phase-error downfalls caused by large output glitches originating from a high-speed accumulator. In addition, a loop-settling monitor is invented to allow the DCO operation mode to be shifted seamlessly and fast. By consuming 9.6 mW, the ADPLL achieves -97 dBc in-band phase noise, -38 dBc/Hz integrated noise, and 740 ns settling time. © 2004-2012 IEEE.
키워드
ADPLL, DCO, loop-settling monitor, metastability, phase noise, phase-error compensator, settling time, TDC
KSP 제안 키워드
All-digital PLL, Dynamic power, Error Correction, Error compensator, Fractional-N PLL, High Speed, High rate, Low-Power, Low-rate, in-band phase noise, operation mode