ETRI-Knowledge Sharing Plaform

ENGLISH

성과물

논문 검색
구분 SCI
연도 ~ 키워드

상세정보

학술지 Presynaptic Spike-Driven Spike Timing-Dependent Plasticity With Address Event Representation for Large-Scale Neuromorphic Systems
Cited 3 time in scopus Download 2 time Share share facebook twitter linkedin kakaostory
저자
박종길, 정상돈
발행일
202006
출처
IEEE Transactions on Circuits and Systems I : Regular Papers, v.67 no.6, pp.1936-1947
ISSN
1549-8328
출판사
IEEE
DOI
https://dx.doi.org/10.1109/TCSI.2020.2966884
협약과제
16ZH1200, 실시간 뉴런-컴퓨터 양방향 통신 및 생체모방 시냅스 기술, 정상돈
초록
Learning plays an important role in the brain to make it adaptive to dynamical environments. This paper presents a presynaptic spike-driven spike timing-dependent plasticity (STDP) learning rule in the address domain for a neuromorphic architecture using a synaptic connectivity table in an external memory at a local routing node. We contribute two aspects to the implementation of the learning rule for extended large-scale neuromorphic systems. First, we reduced buffer sizes required for tracing a spike train which is required to pair all presynaptic and postsynaptic spike for an STDP time window. This method implements an exponential decay STDP function with two parameters: the latest timestamp and the synaptic modification rate at the latest timestamp. It reduces the required buffer size compared to previous works. Second, we resolve a lack of reverse lookup table issue with the presynaptic spike-driven algorithm. The proposed algorithm holds causal updates at postsynaptic spikes until a next presynaptic spike arrival. This approach removes the need of a reverse lookup table required at a postsynaptic spike. We show the implementation of the proposed algorithm in an FPGA device and validate it with a spiking neural network configuration. The experiment results show the proposed algorithm is comparable qualitatively with a conventional STDP learning rule.
키워드
Address domain, column selectivity, reverse lookup table, STDP, synaptic table
KSP 제안 키워드
Address event representation, Buffer Size, Experiment results, FPGA device, Learning rule, Local routing, Modification rate, Network configuration, Neuromorphic architecture, Neuromorphic systems, Spike train