Subjects : engineering design
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Conference | 2010 | Transaction-Level Modeling Simulation Methodology for Semiconductor Chip Design of Star-Mesh Network-on-Chip based on DEVS Formalism 송해상 대한전자공학회 종합 학술 대회 (하계) 2010, pp.1567-1570 |
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| Type | Year | Research Project | Primary Investigator | Download |
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