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구분 출원국
출원년도 ~ 키워드

상세정보

등록 초미세 에스오아이 모스 전계효과 트랜지스터 및 그의 제조방법

초미세 에스오아이 모스 전계효과 트랜지스터 및 그의 제조방법
이미지 확대
발명자
조원주, 이성재, 오지훈, 양종헌, 임기주, 박경완, 장문규
출원번호
10331568 (2002.12.31)
공개번호
20040056307 (2004.03.25)
등록번호
6723587 (2004.04.20)
출원국
미국
협약과제
초록
An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided. The method includes preparing a SOI substrate on which a monocrystalline silicon layer is formed, forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate, forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer, forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening, forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment, forming a gate dielectric layer in the opening on the channel region, forming a gate electrode on the gate dielectric layer to fit in the opening, forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed, forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer, and forming metal interconnections to bury the contact holes.
KSP 제안 키워드
Contact hole, Dielectric materials, Low-Power, Monocrystalline silicon, Power Consumption, SOI MOSFET, SOI substrate, Silicon layer, Small-sized, Source region, dielectric layer, gate dielectric, gate electrode, heat treatment, integration density, low power consumption