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구분 출원국
출원년도 ~ 키워드

상세정보

등록 수직형 채널을 가지는 초미세 MOS 트랜지스터 및 그 제조방법

수직형 채널을 가지는 초미세 MOS  트랜지스터 및 그 제조방법
이미지 확대
발명자
조원주, 박경완, 이성재
출원번호
10617183 (2003.07.11)
공개번호
20040007737 (2004.01.15)
등록번호
6770534 (2004.08.03)
출원국
미국
협약과제
초록
The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface. Then, an annealing process is carried out to diffuse the impurities in the first silicon conductive layer and the second silicon conductive layer into the second single crystal layer, thereby forming a source contact, a drain contact and a vertical channel. Finally, a gate electrode is formed on side walls of the vertical channel.
KSP 제안 키워드
Conductive layer, Crystal silicon, High concentration, Low concentration, MOSFET device, Silicon On Insulator(SOI), Silicon layer, Single crystal, Single-crystal silicon, Vertical MOSFET, Vertical channel, annealing process, gate electrode, insulating layer, small size