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특허 검색
구분 출원국
출원년도 ~ 키워드

상세정보

등록 재구성 가능한 산술연산기 및 이를 구비한 고효율 프로세서

재구성 가능한 산술연산기 및 이를 구비한 고효율 프로세서
이미지 확대
발명자
양일석, 노태문, 석정희, 여준기, 김종대
출원번호
12136107 (2008.06.10)
공개번호
20090150471 (2009.06.11)
등록번호
8150903 (2012.04.03)
출원국
미국
협약과제
초록
Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.
KSP 제안 키워드
Addition operation, Arithmetic unit, Multiplexer (mux), Partial products, Wallace Tree, booth encoder, high efficiency