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구분 출원국
출원년도 ~ 키워드

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등록 전계 효과 트랜지스터의 제조방법

전계 효과 트랜지스터의 제조방법
이미지 확대
발명자
안호균, 임종원, 김해천, 남은수, 윤형섭, 장우진
출원번호
12773216 (2010.05.04)
공개번호
20110143505 (2011.06.16)
등록번호
8053345 (2011.11.08)
출원국
미국
협약과제
초록
Provided is a method for fabricating a field effect transistor. In the method, an active layer and a capping layer are formed on a substrate. A source electrode and a drain electrode is formed on the capping layer. A dielectric interlayer is formed on the substrate, and resist layers having first and second openings with asymmetrical depths are formed on the dielectric interlayer between the source electrode and the drain electrode. The first opening exposes the dielectric interlayer, and the second opening exposes the lowermost of the resist layers. The dielectric interlayer in the bottom of the first opening and the lowermost resist layer under the second opening are simultaneously removed to expose the capping layer to the first opening and expose the dielectric interlayer to the second opening. The capping layer of the first opening is removed to expose the active layer. A metal layer is deposited on the substrate to simultaneously form a gate electrode and a field plate in the first opening and the second opening. The resist layers are removed to lift off the metal layer on the resist layers.
KSP 제안 키워드
Active Layer, Capping layer, Dielectric interlayer, Drain electrode, Field Plate, Field-effect transistors(FETs), field effect, gate electrode, lift-off, metal layer, resist layer
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