상세정보
등록 타임투디지털 컨버터 및 이를 포함하는 완전디지털 위상고정루프
- 출원번호
- 12956498 (2010.11.30)
- 공개번호
- 20110148490 (2011.06.23)
- 등록번호
- 8344772 (2013.01.01)
- 출원국
- 미국
- 협약과제
- 초록
- An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.
- KSP 제안 키워드
- All-digital phase-locked loop(ADPLL), Digital loop filter(DLF), Digitally controlled, Digitally controlled oscillator, Lock Detector, Operational characteristics, Phase Difference, Phase locked loop(PLL), Reference clock, Time-to-Digital Converter, Time-to-digital, all-digital, clock generator, digital converter, digital phase locked loop(DPLL), frequency setting, loop-filter(LF), low-frequency, phase detector(PD), phase error