상세정보
등록 DAC 데이터 변환기의 비선형성을 개선하는 회로 및 구현방법
- 출원번호
- 13854041 (2013.03.29)
- 공개번호
- 20130268572 (2013.10.10)
- 등록번호
- 9378184 (2016.06.28)
- 출원국
- 미국
- 협약과제
- 초록
- Disclosed are an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator. According to the accumulator including a register configured to output input data according to a clock signal; a first adder configured to receive a digital input signal having any bit width and an output signal from the register to perform an add operation; a preset unit configured to output a preset value or a 0 value according to whether a carry of the first adder is generated; and a second adder configured to receive an output signal of the first adder and an output signal of the preset unit to perform the add operation and input the add operation to the register and the data weighted average device including the accumulator, it is possible to improve the nonlinearity occurring in the data converter by generating a number of DAC codes in addition to 2n DAC codes.
- KSP 제안 키워드
- Data Converter, Input signal, Weighted average, clock signal, input data