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성과물

특허 검색
구분 출원국
출원년도 ~ 키워드

상세정보

등록 디지털 위상 고정 루프

디지털 위상 고정 루프
이미지 확대
발명자
부현호, 민병훈, 김천수, 유현규,
출원번호
14028707 (2013.09.17)
공개번호
20140266354 (2014.09.18)
등록번호
9013216 (2015.04.21)
출원국
미국
협약과제
초록
Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.
KSP 제안 키워드
Phase Difference, Phase locked loop(PLL), Reference clock, Signal processor, Time-to-Digital Converter, Time-to-digital, digital converter, digital phase locked loop(DPLL)