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특허 검색
구분 출원국
출원년도 ~ 키워드

상세정보

등록 자기 정렬 박막 트랜지스터 및 그 제조 방법

자기 정렬 박막 트랜지스터 및 그 제조 방법
이미지 확대
발명자
오힘찬, 황치선, 추혜용, 박상희, 피재은, 권오상, 엄인용, 유민기, 박은숙
출원번호
14031100 (2013.09.19)
공개번호
20140145180 (2014.05.29)
등록번호
9252241 (2016.02.02)
출원국
미국
협약과제
초록
Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.
KSP 제안 키워드
Active Layer, Deposition method, Drain electrode, Fabrication method, Gate insulator, Layer pattern, Operation speed, Source and drain, Thin-Film Transistor(TFT), gate electrode, self-Aligned, thin film(TF)
패밀리
 
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구분 특허 출원국 KIPRIS
등록 자기 정렬 박막 트랜지스터 및 그 제조 방법 대한민국 KIPRIS