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출원년도 ~ 키워드

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등록 자기정렬된 트렌치 게이트 전력 소자의 제조방법

자기정렬된 트렌치 게이트 전력 소자의 제조방법
이미지 확대
발명자
박일용, 김종대, 김상기, 구진근, 노태문, 이대우, 양일석
출원번호
10071127 (2002.02.08)
공개번호
20030068864 (2003.04.10)
등록번호
6852597 (2005.02.08)
출원국
미국
협약과제
01MM1700, 휴대단말기용 DC-DC 컨버터 ASIC칩 개발, 김종대
초록
A method for fabricating a power semiconductor device having a trench gate structure is provided. An epitaxial layer of a first conductivity type having a low concentration and a body region of a second conductivity type are sequentially formed on a semiconductor substrate of the first conductivity type having a high concentration. An oxide layer pattern is formed on the body region. A first trench is formed using the oxide layer pattern as an etching mask to perforate a predetermined portion of the body region having a first thickness. A body contact region of the second conductivity type having a high concentration is formed to surround the first trench by impurity ion implantation using the oxide layer pattern as an ion implantation mask. First spacer layers are formed to cover the sidewalls of the first trench and the sidewalls of the oxide layer pattern. A second trench is formed using the oxide layer pattern and the first spacer layers as etching masks to perforate a predetermined portion of the body region having a second thickness greater than the first thickness. A source region of the first conductivity type having a high concentration is formed to surround the second trench by impurity ion implantation using the oxide layer pattern and the first spacer layers as ion implantation masks. Second spacer layers are formed to cover the sidewalls of the second trench and the sidewalls of the first spacer layers. A third trench is formed to a predetermined depth of the epitaxial layer using the oxide layer pattern, the first spacer layers, and the second spacer layers as etching masks. A gate insulating layer is formed in the third trench. A gate conductive pattern is formed in the gate insulating layer. An oxide layer is formed on the gate conductive layer pattern. The first and second spacer layers are removed. A first metal electrode layer is formed to be electrically connected to the source region and the body contact region. A second metal electrode layer is formed to be electrically connected to the gate conductive layer pattern. A third metal electrode layer is formed to be electrically connected to the semiconductor substrate.
KSP 제안 키워드
Body contact(BC), Conductive layer, Conductive pattern, Contact region, Electrode layer, Epitaxial layer, High concentration, Ion implantation, Layer pattern, Low concentration, Oxide layer, Power semiconductor, Second metal, Source region, etching masks, insulating layer, metal electrode, power semiconductor devices, semiconductor device, semiconductor substrate, the body, trench gate