ETRI-Knowledge Sharing Plaform

ENGLISH

성과물

특허 검색
구분 출원국
출원년도 ~ 키워드

상세정보

등록 전력 집적회로 소자의 제조 방법

전력 집적회로 소자의 제조 방법
이미지 확대
발명자
노태문, 김종대, 이대우, 양일석, 박일용, 구진근, 김상기
출원번호
10153975 (2002.05.23)
공개번호
20030119229 (2003.06.26)
등록번호
6855581 (2005.02.15)
출원국
미국
협약과제
01MM1700, 휴대단말기용 DC-DC 컨버터 ASIC칩 개발, 김종대
초록
The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.
KSP 제안 키워드
CMOS devices, Deep well, Electrical isolation, High Voltage, High power, Insulating film, Integrated circuit, Nitride film, Oxide film, Photolithography process, Photoresist film, Power device, SOI structure, Silicon layer, Silicon substrate, annealing process, logic CMOS