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구분 출원국
출원년도 ~ 키워드

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등록 초미세 채널 전계 효과 트랜지스터 및 그 제조방법

초미세 채널 전계 효과 트랜지스터 및 그 제조방법
이미지 확대
발명자
조원주, 양종헌, 안창근, 임기주, 오지훈, 이성재
출원번호
10833452 (2004.04.27)
공개번호
20050009250 (2005.01.13)
등록번호
7195962 (2007.03.27)
출원국
미국
협약과제
03MB1400, 실리콘 미래 신소자 원천 기술 개발, 이성재
초록
Provided is a MOSFET with an ultra short channel length and a method of fabricating the same. The ultra short channel MOSFET has a silicon wire channel region with a three-dimensional structure, and a source/drain junction formed in a silicon conductive layer formed of both sides of the silicon wire channel region. Also, a gate electrode formed on the upper surface of the silicon wire channel region by interposing a gate insulating layer having a high dielectric constant therebetween, and source and drain electrodes connected to the source/drain junction are included. The silicon wire channel region is formed with a triangular or trapezoidal section by taking advantage of different etch rates that depend on the planar orientation of the silicon. The source/drain junction is formed by a solid-state diffusion method.
KSP 제안 키워드
Channel Length, Conductive layer, Dielectric Constant, Etch rates, Field-effect transistors(FETs), High dielectric, High dielectric constant, Planar orientation, Short channel, Short channel MOSFET, Solid-state diffusion, Source and drain, Three dimensional(3D), Three-dimensional structure, diffusion method, dimensional structure, field effect, gate electrode, insulating layer, silicon wire, solid state, source/drain junction