상세정보
등록 박막 트랜지스터의 제조 방법 및 박막 트랜지스터 기판
- 출원번호
- 12507725 (2009.07.22)
- 공개번호
- 20100140706 (2010.06.10)
- 등록번호
- 8119463 (2012.02.21)
- 출원국
- 미국
- 협약과제
- 08MB2900, 모바일 플렉시블 입출력 플랫폼, 조경익
- 초록
- Provided is a method of manufacturing a thin film transistor that can improve self-alignment. In this method, a semiconductor layer comprising a first doped region, a second doped region and a channel region is formed on a sacrificial layer on a first substrate. Next, the semiconductor layer is separated from the first substrate and is then coupled on a second substrate. Next, a dielectric layer is formed on the second substrate and the semiconductor layer, and a first photoresist layer is formed on the dielectric layer. Thereafter, the first photoresist layer is exposed to light from a rear surface of the second substrate by using the first doped region and the second doped region as a mask, to form a first mask pattern. Next, a gate electrode overlapping the channel region is formed on the dielectric layer by using the first mask pattern as a mask, and a source electrode and a drain electrode connected to the first doped region and the second doped region, respectively are formed to complete a thin film transistor.
- KSP 제안 키워드
- Drain electrode, Sacrificial layer, Self-alignment, Thin-Film Transistor(TFT), dielectric layer, gate electrode, rear surface, thin film(TF)
- 패밀리
| 구분 | 특허 | 출원국 | KIPRIS |
|---|---|---|---|
| 등록 | 박막 트랜지스터의 제조 방법 및 박막 트랜지스터 기판 | 미국 |