상세정보
등록 파이프라인 아날로그-디지털 변환기
- 출원번호
- 12777910 (2010.05.11)
- 공개번호
- 20110102220 (2011.05.05)
- 등록번호
- 8164497 (2012.04.24)
- 출원국
- 미국
- 협약과제
- 09MB2100, 45nm급 혼성 SoC용 아날로그 회로기술, 권종기
- 초록
- Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.
- KSP 제안 키워드
- Analog Converter, Analog input, Analog to digital converter(ADC), Chip area, Delay Time, Digital to Analog Converter, Front-End, Input signal, Multiplying Digital-To, Pipeline ADC, Power Consumption, Sample-and-hold amplifier, Sampling error, Sub-ranging ADC, analog-to-digital, digital converter, digital-to-analog(DAC), flash ADC, multiplying digital-to-analog converter(MDAC), sample-and-hold