상세정보
등록 자기 정렬 박막 트랜지스터 및 그 제조 방법
- 출원번호
- 14031100 (2013.09.19)
- 공개번호
- 20140145180 (2014.05.29)
- 등록번호
- 9252241 (2016.02.02)
- 출원국
- 미국
- 협약과제
- 12VB1300, 에너지 절감을 위한 7인치기준 2W급 환경적응 디스플레이 신모드 핵심 원천 기술 개발, 추혜용
- 초록
- Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.
- KSP 제안 키워드
- Active Layer, Deposition method, Drain electrode, Fabrication method, Gate insulator, Layer pattern, Operation speed, Source and drain, Thin-Film Transistor(TFT), gate electrode, self-Aligned, thin film(TF)
- 패밀리
| 구분 | 특허 | 출원국 | KIPRIS |
|---|---|---|---|
| 등록 | 자기 정렬 박막 트랜지스터 및 그 제조 방법 | 대한민국 | KIPRIS |