상세정보
등록 캐시 일관성 유지 장치 및 방법, 이를 이용하는 멀티프로세서 장치
- 출원번호
- 14030543 (2013.09.18)
- 공개번호
- 20140082300 (2014.03.20)
- 등록번호
- 9372795 (2016.06.21)
- 출원국
- 미국
- 협약과제
- 12MD1400, 에너지 스케일러블 벡터 프로세서 선행기술, 엄낙웅
- 초록
- Provided are an apparatus and method for maintaining cache coherency, and a multiprocessor apparatus using the method. The multiprocessor apparatus includes a main memory, a plurality of processors, a plurality of cache memories that are connected to each of the plurality of processors, a memory bus that is connected to the plurality of cache memories and the main memory, and a coherency bus that is connected to the plurality of cache memories to transmit coherency related information between caches. Accordingly, a bandwidth shortage phenomenon may be reduced in an on-chip communication structure, which occurs when using a communication structure between a memory and a cache, and communication for coherency between caches may be simplified.
- KSP 제안 키워드
- Cache Memory, On-chip, On-chip communication, cache coherency, communication structure, main memory
- 패밀리
| 구분 | 특허 | 출원국 | KIPRIS |
|---|---|---|---|
| 등록 | 캐시 일관성 유지 장치 및 방법, 이를 이용하는 멀티프로세서 장치 | 대한민국 | KIPRIS |