ETRI-Knowledge Sharing Plaform

Memory Bandwidth Performance Bottleneck Memory Access Pattern Clock Frequency Memory Address Media Applications Shuffling Algorithm Soft Processor Process Technology Fault-Tolerant Cmos Process Parallel Memory Memory System Conflict Graph Data Reuse Neural Processor Operating Temperature Parallel Processing Physical Memory Access Conflict Transient Error Intellectual Property(IP) Quad-Core Vision Processor Real-Time Test Acceleration Performance Energy Efficiency Error Detection And Correction Embedded Dsp Graphic Processing Unit(GPU) Linked List Processor Architecture Deep Learning(DL) Fault Tolerance High Flexibility Instruction Sets Audio Effects Automotive Vision Error Correction Code Multi-Core Architecture Processor Core Software And Hardware Co-Design Artificial Intelligence Applications Audio Codec Dedicated Hardware Deep Neural Network(DNN) Feature Map Transient Faults True Random Number Memory Page Network Accelerator Power Efficiency System-On-Chip(SoC) Self-Recovering Single Point Superior Performance Digital Audio Effect Development Environment Error Rate Configurable Memory Design Method Development Time High Degree Multi-Core Processor Hardware Design Memory Architecture Overall Performance Low-Power Bonding Process C Language Computing Power Data Cache Duty Cycle(DC) Embedded Media Electronic Systems High-Performance Computing Systems Heterogenous System Kernel Weights Labeled Data Memory Interface Multi-Fpga Offset Calibration Power Consumption Object Recognition On-Chip Memory Power Saving Software Profiling State-Of-Art Data Alignment Autonomous Cars Convolution Neural Network(CNN) Execution Time Effect System Floating-Point Data Graph Construction Image Recognition User-Friendly Mesh Structure Max-Pooling Need For Optimization Analysis Parallel Programming Model Programming Models Pseudo-Random Recovery Rate Risc Core Electronic Control Unit(ECU) Beta Source Coupled With Electronics System Event-Based Fixed-Point General-Purpose Graphics Processing Unit(GPGPU) In-Memory In-Vehicle Low-If Many-Core Near Threshold Voltage Power Limit Power Model Optimization Algorithm Power Dissipation Road Vehicle Resource Utilization Raster-Scan Safety Mechanism State-Of-The-Art Vehicle Safety Automated Optimization Audio Processing Dynamic Voltage And Frequency Scaling Dynamic Frequency Scaling Dependent Failures Eureka-147 Embedded System Hardware Complexity Higher Performance Input And Output Ultra-Low-Energy Large Memory Linear Systems Mobile Media Memory Structure Matrix Distribution Power Source Quantitative Analysis Reconfigurable System Scientific Publishing Soc System Small Footprint Analog To Digital Converter(ADC) Verilog Rtl Automotive Electronics Digital Signal Processor(DSP) Design Verification Experimental Result Error Prediction Fpga Simulation Fault Performance Function Call High Throughput(HTP) Heterogeneous Systems Iso 26262 Real-Time Execution Matrix Multiplication Large-Scale Micro-Processor Memory Modules Mobile Application(APP) Neural Network Applications Operating Frequency Performance Analysis Permanent Faults Run Time Silicon Wafer Scan Order Safety Requirements Energy-Efficient Area Constraints Virtualized System 28nm Cmos Technology Application-Specific Best Performance Control Scheme Computing Performance C Code External Memory Error Recovery Estimated Performance Flow Control Fpga Platform Internet Of Things Applications Processing Platform Multi-Dimensional Neural Processing Power Behavior Operating Energy Reconfigurable Cache Safe Design Data Processing Virtual Platform System-On-A-Chip Autonomous Driving Vehicle Adaptive Power Baseband Processor Code Size Digital Multimedia Broadcasting Embedded Applications Fault Injector Functional Safety Fpga Board Graph Pattern Flexible Memory Homogeneous Systems Heterogeneous Integration Integration Platform Total Power Learning Application Linear System Of Equations Linux Device Driver Maximum Frequency Operating Scheme Pipelined Adc Process Level Proposed Work Programmable Control Parameter Optimization Rtl Simulation Software Implementation System Development Platform Speed-Up Safety Standard Voltage Scaling Wide Range C Program Digital Audio Broadcasting Efficient Architecture Fault Injection Failure Rate Hardware Overhead Hardware Implementation High Frequency(HF) High Speed Improved Performance 0.18um Cmos Lu Decomposition Memory-Efficient Power Management Optimization Methods Pre-Emphasis Performance Emulation Systolic Array Supply Voltage Single-Chip Silicon Area Voice Recognition