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학술지 Comparative Studies on Electrical Bias Temperature Instabilities of In-Ga-Zn-O Thin Film Transistors with Different Device Configurations
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저자
유민기, 박상희, 황치선, 윤성민
발행일
201311
출처
Solid-State Electronics, v.89, pp.171-176
ISSN
0038-1101
출판사
Elsevier
DOI
https://dx.doi.org/10.1016/j.sse.2013.08.008
협약과제
13VB2100, 고품위 plastic AMOLED 원천 기술 개발, 박상희
초록
We investigated the effect of positive bias temperature stress (PBTS) on the device stabilities of In-Ga-Zn-O thin film transistors with bottom gate and top gate structures. Under the PBTS conditions at the gate voltage of +20 V and the temperature of 60 C, the turn-on voltage experienced a negative shift of -1.5 V for the top gate device, while a larger positive shift of 3.0 V was observed for the bottom gate device. From the variations in transfer characteristics at various temperatures and the discussions on the thermal activation energy, it was suggested that these different behaviors of two devices originated from interface trap densities caused by the plasma damage and the pinning of Fermi energy level for the bottom and top gate devices, respectively. It was very encouraging that the variation of the turn-on voltage could be minimized when the top gate device was fabricated to have a very controlled interface. © 2013 Elsevier Ltd. All rights reserved.
키워드
Bottom-gate, In-Ga-Zn-O (IGZO), Oxide semiconductor, Thin-film transistor, Top-gate
KSP 제안 키워드
Bias temperature stress, Bottom gate, Device stability, Fermi energy level, In-Ga-Zn-O(IGZO), Negative shift, Oxide semiconductor, Positive bias, Thermal activation energy, Thin-Film Transistor(TFT), Turn-on voltage