ETRI-Knowledge Sharing Plaform

ENGLISH

성과물

논문 검색
구분 SCI
연도 ~ 키워드

상세정보

학술지 A Design of Low Latency Random Access Preamble Detector for LTE Uplink Receiver
Cited 0 time in scopus Download 6 time Share share facebook twitter linkedin kakaostory
저자
이주현, 구본태, 이혁재
발행일
201305
출처
IEICE Transactions on Communications, v.E96.B no.5, pp.1089-1096
ISSN
0916-8516
출판사
일본, 전자정보통신학회 (IEICE)
DOI
https://dx.doi.org/10.1587/transcom.E96.B.1089
협약과제
12MD1500, 3G LTE 기반 All-In-One FemtoCell 기지국 SoC 플랫폼, 구본태
초록
This paper presents a hardware design of high throughput, low latency preamble detector for 3GPP LTE physical random access channel (PRACH) receiver. The presented PRACH receiver uses the pipelined structure to improve the throughput of power delay profile (PDP) generation which is executed multiple times during the preamble detection. In addition, to reduce detection latency, we propose an instantaneous preamble detection method for both restricted and unrestricted set. The proposed preamble detection method can detect all existing preambles directly and instantaneously from PDP output while conducting PDP combining for restricted set. The PDP combining enables the PRACH receiver to detect preambles robustly even in severe Doppler effect or frequency error exist. Using proposed method, the worst case preamble detection latency time can be less than 1ms with 136MHz clock and the proposed PRACH receiver can be implemented with approximately 237k equivalent ASIC gates count or occupying 30.2% of xc6vlx130t FPGA device. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.
키워드
Latency, LTE, PRACH, Random access, Throughput, Uplink
KSP 제안 키워드
3GPP LTE, Detection Method, Detection latency, FPGA device, Hardware Design, High throughput(HTP), Information and communication, LTE uplink, Latency time, Low latency, Physical random access channel(PRACH)