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학술지 A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique
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저자
조영균, 전영득, 남재원, 권종기
발행일
201012
출처
IEEE Transactions on Circuits and Systems II : Express Briefs, v.57 no.7, pp.502-506
ISSN
1549-7747
출판사
IEEE
DOI
https://dx.doi.org/10.1109/TCSII.2010.2048387
협약과제
09MB2100, 45nm급 혼성 SoC용 아날로그 회로기술, 권종기
초록
A 9-bit 80 MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low power and a small area, is presented. The 9-bit capacitor array consists of only 16 unit capacitors and a coupling capacitor due to the proposed binary-weighted split-capacitor arrays with a merged-capacitor switching technique. The proposed ADC includes a comparator with offset cancellation and uses digital calibration for error correction. The ADC is implemented in a 65-nm complimentary metaloxidesemiconductor technology and occupies an active area of 0.068 mm2 with a reference buffer. The differential and integral nonlinearities of the ADC are less than 0.37 and 0.40 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 50.71 dB, a spurious-free dynamic range of 66.72 dB, and an effective number of bits of 8.13 bits with a 78 MHz sinusoidal input at 80 MS/s. The ADC consumes 3.4 mW with the reference buffer at a 1.0-V supply and achieves a figure of merit of 78 fJ/conversion step. © 2006 IEEE.
키워드
Error correction, merged-capacitor switching (MCS), offset cancellation, split-capacitor array, successive approximation register (SAR) analog-to-digital converter (ADC)
KSP 제안 키워드
Active area, Analog to digital converter(ADC), Capacitor array, Capacitor switching, Distortion ratio, Effective Number of Bits, Error Correction, Figure of merit, Low-Power, Reduction technique, Signal-to-Noise