BROWSE
Detail
Journal Article
Low-Noise Wideband PLL with Dual-Mode Ring-VCO
Cited 10 time in 
Download 3 time
Share 
Download 3 time
Share
- Authors
- H.D. Lee, S.-J. Yun, K.-D. Kim, J.-K. Kwon
- Issue Date
- 2010-09
- Citation
- Electronics Letters, v.46, no.20, pp.1368-1370
- ISSN
- 0013-5194
- Publisher
- IET
- Language
- English
- Type
- Journal Article
- Project Code
- 10MB1700, Development of Analog Circuit Techniques for Mixed SoC based on 45nm CMOS Technology, Kwon Jong-Kee
- Abstract
- A low-jitter 110MHz-to-620MHz phase-locked loop (PLL) that includes a low-noise wide-frequency-range ring oscillator with a dual-mode operation is presented. The measurement results using a 65nm low-power CMOS process show that the proposed PLL achieves as low as a 2.5ps RMS jitter at 600MHz of output frequency while consuming 2.7mW at a 1.2V supply. The die area is only 0.09mm2. © 2010 The Institution of Engineering and Technology.
- KSP Keywords
- CMOS Process, Dual-mode ring, Low noise, Output frequency, Phase locked loop(PLL), Wide frequency, dual-mode operation, low jitter, low-power CMOS, measurement results, ring oscillator