ETRI-Knowledge Sharing Plaform

ENGLISH

성과물

논문 검색
구분 SCI
연도 ~ 키워드

상세정보

학술지 High-Density Nano-Scale N-Channel Trench-Gated MOSFETs Using the Self-Aligned Technique
Cited 3 time in scopus Download 0 time Share share facebook twitter linkedin kakaostory
저자
김상기, 김종대, 구진근, 양일석, 이진호, 박훈수, Kyou-Ho Lee
발행일
201010
출처
Journal of the Korean Physical Society, v.57 no.4, pp.802-805
ISSN
0374-4884
출판사
한국물리학회 (KPS)
DOI
https://dx.doi.org/10.3938/jkps.57.802
협약과제
10MB3600, BLDC 모터용 고전압/대전류 파워모듈 및 ESD기술개발, 김종대
초록
We propose a novel process technology for fabricating a very high density n-channel trench-gate metal oxide silicon field effect transistor (MOSFET) by using an oxide spacer and self-aligned techniques. Due to this nano-scale technology, the cell pitch of the trench-gate MOSFET could be reduced to 3.0 μm, which resulted in an increase in the cell density and in current driving capability. By reducing masks to four layers, a cost-effective process was available. The self-aligned technique also permits a narrow width of the trench gate on the scale of 300 nm. The fabricated device exhibits a specific on-resistance of 1.4 m廓쨌cm2 for a breakdown voltage of 114.8 V. Moreover, the long-term gate oxide's integrity was improved by adopting corner rounding and hydrogen annealing technologies.
키워드
Self-aligned technique, Specific on-resistance, Trench-gated MOSFET
KSP 제안 키워드
Breakdown voltage(BDV), Cell density, Corner rounding, Field-effect transistors(FETs), Gate oxide, High-density, Hydrogen annealing, Metal-oxide(MOX), Metal-oxide-semiconductor field-effect transistor(MOSFET), N-channel, Novel process