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학술지 Compensation Technique for Time Alignment of Envelope and Phase Paths in an Envelope Delta-sigma Modulator
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저자
이성준, 조영균, 정재호
발행일
201506
출처
IEICE Electronics Express, v.12 no.13, pp.1-6
ISSN
1349-2543
출판사
IEICE
DOI
https://dx.doi.org/10.1587/elex.12.20150372
협약과제
14MI8100, 밀리미터파 5G 이동통신 시스템 개발, 김태중
초록
A compensation technique for time alignment of envelope and phase paths in an envelope delta-sigma modulator (EDSM) is proposed. In this technique, two controllable delays are intentionally added, and a combination of the two delays compensates a time misalignment caused by the inherent processing delay of a delta-sigma modulator (DSM) and the difference of propagation delays on the asymmetric envelope and phase paths. One of the two delays is a digital sample delay, which is added in the digital domain before a digital-to-analog converter (DAC). The other delay is obtained by the use of D flip flops (DFFs) followed by a DSM, which is possible because the output of a DSM is changed by a clock. The validity of the proposed technique is confirmed by simulation.
키워드
Class-S power amplifier, Envelope delta-sigma modulator, Time alignment
KSP 제안 키워드
Class-S power amplifier, Delta-Sigma Modulator, Digital to Analog Converter, Flip-flop, Processing Delay, Propagation delay, Sample Delay, Time Misalignment, compensation technique, digital domain, digital-to-analog(DAC)