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학술지 Low-Power Digital PLL Based TDC Using Low Rate Clocks
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저자
박미정, 이자열, 부현호, 민병훈, 김성도, 박문양, 이창석, 유현규
발행일
201107
출처
Electronics Letters, v.47 no.14, pp.793-794
ISSN
0013-5194
출판사
IET
DOI
https://dx.doi.org/10.1049/el.2011.1426
협약과제
11MB1500, 차세대 무선 융합 단말용 Advanced Digital RF 기술 개발, 유현규
초록
A time-to-digital converter (TDC) using a low rate clock is presented. A simple TDC, capable of decreasing power consumption and solving the metastability problem by using low-rate clocks to detect the fine fractional time difference between the reference clock and digitally controlled oscillator (DCO) clock, is presented. The proposed TDC also includes a simple DCO clock period (Tv) calculation algorithm. An all-digital phase-locked loop (ADPLL), fabricated in 90nm CMOS process, dissipates 0.8mA at 1.2V, and achieves 6.25ps period RMS jitter from 2GHz. © 2011 The Institution of Engineering and Technology.
KSP 제안 키워드
All-digital phase-locked loop(ADPLL), CMOS Process, Calculation algorithm, Clock Period, Digital PLL, Digitally controlled oscillator, Low-Power, Low-rate, Phase locked loop(PLL), Power Consumption, Reference clock