ETRI-Knowledge Sharing Plaform

ENGLISH

성과물

논문 검색
구분 SCI
연도 ~ 키워드

상세정보

학술지 Asynchronous 2-Phase Protocol Based on Ternary Encoding for On-Chip Interconnect
Cited 4 time in scopus Download 1 time Share share facebook twitter linkedin kakaostory
저자
오명훈, 김성운
발행일
201110
출처
ETRI Journal, v.33 no.5, pp.822-825
ISSN
1225-6463
출판사
한국전자통신연구원 (ETRI)
DOI
https://dx.doi.org/10.4218/etrij.11.0211.0063
협약과제
10ZB1100, 융.복합부품 핵심기술 연구, 남은수
초록
Level-encoded dual-rail (LEDR) has been widely used in onchip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current-mode multiple valued logics. Using 0.25 μm CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power-delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz. © 2011 Optical Society of America.
키워드
Asynchronous handshake protocol, Multiple-valued logic, Ternary encoding
KSP 제안 키워드
100 MHz, Asynchronous handshake, CMOS Technology, Current-mode(CM), Data transfer, Dual-rail, Encoder and Decoder, Global interconnects, Handshake Protocol, Multiple-Valued Logic(MVL), Reduction ratio