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학술지 A Cable Modem Receiver Supporting Four Upstream Channels
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이재호, 최동준, 이수인, 김환우
IEEE Transactions on Consumer Electronics, v.57 no.3, pp.1105-1111
11PR3600, 차세대 디지털 케이블 전송기술 개발, 최동준
A receiver of upstream cable modem (CM) for data over cable service interface specifications (DOCSIS) 3.0 is proposed and implemented in field programmable gate arrays (FPGAs). The receiver, which can demodulate four upstream channels simultaneously, consists of a digital down converter (DDC), a pre-forward error correction (FEC) and a FEC decoder. In DDC, fixed decimation and variable decimation with respect to symbol rate are used to remove adjacent channel images. An automatic gain control (AGC) uses a power calculation in a packet detection (PD) to reduce hardware complexity. Coefficients of symbol timing estimation (STE) use the sign of preamble symbols for eliminating multipliers. In addition, STE operates only for some parts of preamble to save power consumption. We simulate estimated AGC values, success probability of STE, estimated frequency offsets. In addition, it is found that when the bit error rate (BER) of the pre-FEC of 64QAM is 10-5, the required Eb/N0 is 19.5 dB under the conditions of additive white Gaussian noise (AWGN), a frequency offset, and echo channel. We measure the spectrum of DDC output, an estimated AGC value, and an estimated frequency offset, and experiment on FEC decoder. Measured results show the maximum transmitted error vector magnitude (EVM) of 1.54 % and the maximum received EVM of 2.67%. © 2006 IEEE.
bit error rate of pre-FEC, Cable modem receiver, DOCSIS 3.0, errorvector magnitude
KSP 제안 키워드
Additive white Gaussian noise(AWGN), Adjacent channel, Automatic Gain Control(AGC), Bit Error Rate(And BER), Data over cable service interface specifications(DOCSIS), Digital Down Converter, Estimated frequency, Field Programmable Gate Arrays(FPGA), Forward error correction(FEC), Hardware complexity, Power Consumption