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학술지 Multi-bit Sigma-Delta Modulator for Low Distortion and High-Speed Operation
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저자
김이경, 권종기
발행일
200712
출처
ETRI Journal, v.29 no.6, pp.835-837
ISSN
1225-6463
출판사
한국전자통신연구원 (ETRI)
DOI
https://dx.doi.org/10.4218/etrij.07.0207.0140
협약과제
07MB2600, 유비쿼터스 단말용 부품 모듈, 김종대
초록
A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to-digital converter and the scrambler logic. Implemented by a 0.13 μm CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1dB for -6 dBFS input signal.
키워드
Feed-forward topology, Low distortion, Low voltage, Multi-bit sigma-delta modulator
KSP 제안 키워드
Analog to digital converter(ADC), CMOS Process, Feedback Paths(FBP), Input signal, feed-forward topology, high linearity, high-speed operation, low voltage, low-distortion, sigma-delta modulator, spurious-free dynamic range(SFDR)