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학술지 A 10-bit 205-MS/s 1.0- mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications
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저자
이승철, 전영득, 권종기, 김종대
발행일
200712
출처
IEEE Journal of Solid-State Circuits, v.42 no.12, pp.2688-2695
ISSN
0018-9200
출판사
IEEE
DOI
https://dx.doi.org/10.1109/JSSC.2007.908760
협약과제
07MB2600, 유비쿼터스 단말용 부품 모듈, 김종대
초록
This paper describes a 10-bit 205-MS/s pipeline analog-to-digital converter (ADC) for flat panel display applications with the techniques to alleviate the design limitations in the deep-submicron CMOS process. The switched source follower combined with a resistor-switch ladder eliminates the sampling switches and achieves high linearity for a large single-ended input signal. Multistage amplifiers adopting the complementary common-source topology increase the output swing range with lower transconductance variation and reduce the power consumption. The supply voltage for the analog blocks is provided by the low drop-out regulator for a high power-supply rejection ratio (PSRR) under the noisy operation environment. The pipeline stages of the ADC are optimized in the aspect of power consumption through the iterated calculation of the sampling capacitance and transconductance. The ADC occupies an active area of 1.0 mm in a 90-nm CMOS process and achieves a 53-dB PSRR for a 100-MHz noise tone with the regulator and a 55.2-dB signal-to-noise-and-distortion ratio for a 30-MHz 1.0-V single-ended input at 205 MS/s. The ADC core dissipates 40 mW from a 1.0-V nonregulated supply voltage. © 2007 IEEE.
키워드
Amplifiers, Analog-to-digital converter (ADC), Buffer circuits, CMOS analog integrated circuits, Integrated circuit testing, Low drop-out regulator, Low power, Low voltage, Noise measurement, Pipeline stage optimization, Power-supply rejection ratio (PSRR), Sample-and-hold (S/H) circuits, Switched-capacitor circuits
KSP 제안 키워드
90-nm, Active area, Analog to digital converter(ADC), Buffer circuits, CMOS Process, CMOS analog integrated circuits, Display applications, Distortion ratio, High power, Input signal, Low drop-out(LDO)