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학술지 Fast-Lock Hybrid PLL Combining Fractional- N and Integer-N Modes of Differing Bandwidths
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저자
Kyoung Ho Woo, Yong Liu, 남은수, Don Hee Ham
발행일
200802
출처
IEEE Journal of Solid-State Circuits, v.43 no.2, pp.379-389
ISSN
0018-9200
출판사
IEEE
DOI
https://dx.doi.org/10.1109/JSSC.2007.914281
협약과제
07DB1100, 3차원 거리/영상 신호처리 집적화 회로를 내장한 InGaAs 광검출 수신기, 김호영
초록
We introduce a single-loop PLL that operates in a narrower-bandwidth, integer- mode during phase lock and in a wider-bandwidth, fractional-N mode during transient. This hybrid PLL, as a generalization of the conventional variable-bandwidth PLL that shins only its bandwidth, simultaneously achieves the fast-locking advantage of the fractional-N PLL and design simplicity of the integer-N PLL, and as such, brings benefits in certain important PLL applications. In addition, the frequency division mode switching, unique in the hybrid PLL, enables a new, more digital protocol to execute bandwidth switching. A CMOS IC prototype attests to the validity of the proposed approach. © 2008 IEEE.
키워드
Charge-pump phase-locked loops, Fractional-N frequency synthesizers, Integer-N frequency synthesizers, Phase-locked loops
KSP 제안 키워드
Bandwidth Switching, CMOS IC, Charge pump, Fractional-N PLL, Frequency division, Frequency synthesizer, Phase locked loop(PLL), Single-loop, Variable bandwidth, fast-locking, integer-n