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학술지 A 0.9-V 60-μW 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range
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저자
노정진, 변산호, 최영길, 노형동, 김이경, 권종기
발행일
200802
출처
IEEE Journal of Solid-State Circuits, v.43 no.2, pp.361-370
ISSN
0018-9200
출판사
IEEE
DOI
https://dx.doi.org/10.1109/JSSC.2007.914266
협약과제
07MB2600, 유비쿼터스 단말용 부품 모듈, 김종대
초록
A 0.9-V 60-μW delta-sigma modulator is designed using standard CMOS 0.13-μm technology. The modulator achieves 83-dB dynamic range in a signal bandwidth of 20 kHz with a sampling frequency of 2 MHz. The input-feedforward architecture is used to reduce the voltage swing of the integrators, which enables low-power amplifiers. By considering the characteristics of the modulator architecture, low-quiescent operational transconductance amplifiers are designed, which use positive feedback to increase dc gain. The designed modulator shows very high figure of merit among the state-of-the-art sub-1-V modulators. © 2008 IEEE.
키워드
Low power, Low voltage, Operational transconductance amplifier, Sigma-delta modulation, Switched capacitator circuits
KSP 제안 키워드
DC gain, Delta-Sigma Modulator, Low-Power, Operational transconductance amplifier, Positive Feedback, Sampling frequency, Sigma-delta modulation, Voltage swing, dynamic range, fourth-order, high figure of merit