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High-gain and Low-hysteresis Properties of Organic Inverters with an UV-photo Patternable Gate Dielectrics
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- Authors
- Sang Chul Lim, Seong Hyun Kim, Gi Heon Kim, Jae Bon Koo, Yong Suk Yang, Jung Hun Lee, Chan Hoe Ku, Yoon-Ho Song
- Issue Date
- 2008-04
- Citation
- Thin Solid Films, v.516, no.12, pp.4330-4333
- ISSN
- 0040-6090
- Publisher
- Elsevier
- Language
- English
- Type
- Journal Article
- Abstract
- Low-hysteresis properties for an organic thin-film transistor (OTFTs) and a high-gain inverter were fabricated using a self-synthesized UV-photo patternable gate dielectric. The hysteresis behavior was not observed in the transfer characteristics of OTFTs or in the voltage transfer characteristics of the organic inverter. For a given dielectric thickness and applied voltage, pentacene OTFTs with inverter circuits were characterized by the field effect mobility, the on/off current ratio, threshold voltage (Vth), and the gain. The field effect mobility, Vth and the on/off currents ratio were 0.03혻cm2/Vs,- 3.3혻V and 106, respectively. The inverter has very large gain of 32 and matching input and output levels, despite having a positive switch-on voltage and slight hysteresis. From OTFT device and inverter circuit measurements, it was found that the hysteresis behavior was caused by the interface-state charge trapping between the gate dielectric and the pentacene semiconductor layer. © 2007 Elsevier B.V. All rights reserved.
- KSP Keywords
- Charge trapping, Dielectric thickness, High Gain, Hysteresis behavior, Hysteresis properties, Input-Output, Inverter circuit, Large gain, Low hysteresis, Self-synthesized, Thin-Film Transistor(TFT)