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학술지 Negative Offset Operation of Four-Transistor CMOS Image Pixels for Increased Well Capacity and Suppressed Dark Current
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저자
민봉기, 송영주, Albert J. P. Theuwissen
발행일
200804
출처
IEEE Electron Device Letters, v.29 no.4, pp.347-349
ISSN
0741-3106
출판사
IEEE
DOI
https://dx.doi.org/10.1109/LED.2008.917812
초록
This letter presents an electrical method to reduce dark current as well as increase well capacity of four-transistor pixels in a CMOS image sensor, utilizing a small negative offset voltage to the gate of the transfer (TX) transistor particularly only when the TX transistor is off. As a result, using a commercial pixel in a 0.18 μm CMOS process, the voltage drop due to dark current of the pinned photodiode (PPD) is reduced by 6.1 dB and the well capacity is enhanced by 4.4 dB, which is attributed to the accumulated holes and the increased potential barrier near the PPD, respectively. © 2008 IEEE.
키워드
CMOS image sensor (CIS), Dark current, Four-transistor pixel, Hole accumulation diode, Imager, Pinned photodiode (PPD), Well capacity
KSP 제안 키워드
CMOS Process, CMOS image sensor, Dark Current, Pinned photodiode, Potential barrier, Voltage Drop, electrical method, hole accumulation, image pixels, offset voltage