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학술지 A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator
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저자
성창경, 이승우, 최우영
발행일
200805
출처
IEICE Transactions on Communications, v.E91-B no.5, pp.1397-1402
ISSN
0916-8516
출판사
일본, 전자정보통신학회 (IEICE)
DOI
https://dx.doi.org/10.1093/ietcom/e91-b.5.1397
협약과제
08MR2400, 멀티미디어 컨버전스 네트워크 온칩 기술 개발, 이범철
초록
We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-m CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231 - 1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.Copyright © 2008 The Institute of Electronics, Information and Communication Engineers.
키워드
Burst-mode, Clock and data recovery circuit, Digital phase aligner, Phase interpolator
KSP 제안 키워드
CMOS Technology, Clock and Data Recovery Circuit(CDR), Information and communication, Run length, bit error, burst mode, frequency offset, input data, long sequence, measurement results, phase interpolator