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학술대회 Application-Adaptive Reconfiguration of Memory Address Shuffler for FPGA-Embedded Instruction-Set Processor
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저자
권영수, 구본태, 엄낙웅
발행일
200809
출처
International Conference on Field Programmable Logic and Applications (FPL) 2008, pp.209-214
DOI
https://dx.doi.org/10.1109/FPL.2008.4629933
협약과제
08MB2500, 오디오 비디오 신호처리용 임베디드 DSP Platform, 엄낙웅
초록
Programmability requirement in reconfigurabie systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, the memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler to be integrated in the memory access arbiter for the parallel memory system in a soft processor. The novel address shuffling algorithm reallocates the decomposed memory sub-pages based on the access conflict graph obtained by profiling the memory access pattern of the application to produce the synthesizable code. The address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that the amount of simultaneous accesses to the identical physical memory block diminishes. The reconfigurebility of the address shuffler enables the adaptive address shuffling depending on the memory access pattern of an application running on the soft processor. The configurable address shuffler reduces the amount of access conflicts by 80% on average utilizing 1592 LUTs which is 14% of that of the processor. ©2088 IEEE.
KSP 제안 키워드
Access Conflict, Configurable memory, Instruction sets, Media applications, Memory System, Memory access pattern, Memory address, Memory bandwidth, Overall performance, Parallel memory, Physical Memory