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학술대회 Design of High Energy Efficiency 32bit Processing Unit Using Instruction-Levels Data Gating and Dynamic Voltage Scaling techniques
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저자
양일석, 노태문, 여순일, 권우현, 김종대
발행일
200811
출처
International SoC Design Conference (ISOCC) 2008, pp.II-69-II-72
DOI
https://dx.doi.org/10.1109/SOCDC.2008.4815686
협약과제
08MB1800, 유비쿼터스 단말용 부품 모듈, 김종대
초록
This paper describes design and circuit simulation of the high energy efficiency 32bit processing unit (PU) using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating and DVS technique. We can control activation and switching activity of the function units using the proposed data gating technique and we can control powers of the function units using the proposed DVS technique. We simulated the power and circuit simulation for running test program using Spectra with layout extraction data which does not include PAD. We selected the optimum reduced power supply to 0.667 times of the supplied power supply in this paper. The energy efficiency of the proposed 32bit processing unit using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32bit processing unit without using instruction-levels data gating and DVS techniques. The energy efficiency of the proposed instruction-level DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system but a hardware implementation is very easy. The designed high energy efficiency 32bit processing unit can utilize as the coprocessor processing massive data at high speed. © 2008 IEEE.
키워드
And data gating technique, Dynamic voltage scaling technique, Energy efficiency, Processing unit
KSP 제안 키워드
DC-DC Converters, Data gating, Dynamic voltage scaling, Gating technique, Hardware Implementation, High Speed, Massive Data, Processing unit, Switching activity, circuit simulation, high energy efficiency