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학술지 Sub-30 nm Gate Template Fabrication for Nanoimprint Lithography Using Spacer Patterning Technology
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저자
박건식, 백규하, 김동표, 우종창, 노광수, 이기준, 도이미
발행일
201102
출처
Journal of Nanoscience and Nanotechnology, v.11 no.2, pp.1625-1628
ISSN
1533-4880
출판사
American Scientific Publishers (ASP)
DOI
https://dx.doi.org/10.1166/jnn.2011.3379
초록
In this study, we present a spacer patterning technology for sub-30 nm gate template which is used for nano-scale MOSFETs fabrication. A spacer patterning technology using a poly-silicon microfeature and a chemical vapor deposition (CVD) SiO 2 spacer has been developed, and the sub-30 nm structures by conventional dry etching and chemical mechanical polishing are demonstrated. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields a large-area template with critical dimension of minimum-sized features much smaller than that achieved by optical lithography. Copyright © 2011 American Scientific Publishers All rights reserved.
키워드
Nanoimprint lithography, Spacer patterning technology, Template
KSP 제안 키워드
Chemical Mechanical Polishing(CMP), Chemical Vapor Deposition, Critical dimension, Optical lithography, Poly-silicon, SiO 2, Sub-30 nm structures, Template fabrication, dry etching, film thickness, large area