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학술지 Fabrication of N-type Schottky Barrier Thin-film Transistor with Channel Length and Width of 0.1 μm and Erbium Silicide Source/Drain
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저자
양종헌, 안창근, 백인복, 장문규, 성건용, 박병철, 임기주, 이성재
발행일
200901
출처
Thin Solid Films, v.517 no.5, pp.1825-1828
ISSN
0040-6090
출판사
Elsevier
DOI
https://dx.doi.org/10.1016/j.tsf.2008.09.072
협약과제
08MC4400, 가정용 고감도 배뇨분석 센서 모듈, 성건용
초록
In this paper, a Schottky barrier polycrystalline silicon thin-film transistor (SB TFT) with erbium silicide source/drain is demonstrated using low temperature processes. A low temperature oxide is used for a gate dielectric and the transistor channel is crystallized by a metal-induced lateral crystallization process. An n-type SB TFT shows a normal electrical performance with subthreshold slope of 239 mV/dec, ION/IOFF ratio of 5.8 × 104 and ION of 2혻μA/μm at VG = 3혻V, VD = 2.5혻V for 0.1혻μm device. A process temperature is maintained at less than 600 °C throughout the whole processes. The SB TFT is expected to be a promising candidate for a next system-on-glass technology and an alternative 3D integration technology. © 2008 Elsevier B.V. All rights reserved.
키워드
3D integration, Erbium silicide, Low temperature poly-Si, SB TFT, Schottky barrier, Thin-film transistor
KSP 제안 키워드
3D integration technology, Channel Length, Erbium silicide, Low temperature(LT), Low temperature poly-Si, Low-temperature process, Metal-induced lateral crystallization, N-type, Polycrystalline silicon(poly-Si), Polycrystalline silicon thin-film transistor, Process temperature