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학술지 Impact of Device Configuration on the Temperature Instability of Al-Zn-Sn-O thin Film Transistors
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저자
정재경, 양신혁, 조두희, 박상희, 황치선, 조경익
발행일
200910
출처
Applied Physics Letters, v.95 no.12, pp.123505-1-123505-3
ISSN
0003-6951
출판사
American Institute of Physics (AIP)
DOI
https://dx.doi.org/10.1063/1.3236694
협약과제
09MB2900, 투명전자 소자를 이용한 스마트 창, 조경익
초록
We compared the effect of the temperature on the device stability of Al-Zn-Sn-O (AZTO) thin film transistors (TFTs) with top gate and bottom gate architectures. While the bottom gate device without any passivation layer on the AZTO channel layer showed a large threshold voltage (Vth) shift of 1.6 V after heating it from 298 to 398 K, the naturally passivated top gate device exhibited a smaller Vth shift of 0.6 V. This different behavior is discussed based on the concept of the thermal activation energy of the subthreshold drain current. It is proposed that the suitable passivation and lower interfacial trap density for the top gate TFT are responsible for its superior temperature stability compared to the bottom gate device. © 2009 American Institute of Physics.
KSP 제안 키워드
Al-Zn, Bottom gate, Channel layer, Device configuration, Device stability, Drain current, Interfacial trap, Temperature stability, Thermal activation energy, Thin-Film Transistor(TFT), Vth shift