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학술지 A 0.6-V Delta-Sigma Modulator With Subthreshold-Leakage Suppression Switches
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저자
노형동, 김형중, 최형길, 노정진, 김이경, 권종기
발행일
200911
출처
IEEE Transactions on Circuits and Systems II : Express Briefs, v.56 no.11, pp.825-829
ISSN
1549-7747
출판사
IEEE
DOI
https://dx.doi.org/10.1109/TCSII.2009.2032444
협약과제
09MB2100, 45nm급 혼성 SoC용 아날로그 회로기술, 권종기
초록
A 0.6-V 34-μW delta-sigma modulator implemented by using a standard 0.13-μm complementary metaloxidesemiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order deltasigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 μWfor the modulator, and the core chip size is 0.33 mm2. © 2009 IEEE.
키워드
Analog-to-digital converter (ADC), Deltasigma modulator, Harmonic distortion, Leakage current, Signal-to-noiseplus-distortion ratio (SNDR), Switched-capacitor circuit
KSP 제안 키워드
Analog to digital converter(ADC), Core-Chip, Delta-Sigma Modulator, Distortion ratio, High performance, Input feedforward, Leakage current, Leakage suppression, Peak-Signal-to-Noise-Ratio(PSNR), Power Consumption, Signal noise ratio(SNR)