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학술지 Effects of Interfacial Dielectric Layers on the Electrical Performance of Top-Gate In-Ga-Zn-Oxide Thin-Film Transistors
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저자
정우석, 이정민, 이종호, 박상희, 윤성민, 변춘원, 양신혁, 정승묵, 조경익, 황치선
발행일
200912
출처
ETRI Journal, v.31 no.6, pp.660-666
ISSN
1225-6463
출판사
한국전자통신연구원 (ETRI)
DOI
https://dx.doi.org/10.4218/etrij.09.1209.0049
협약과제
09MB2900, 투명전자 소자를 이용한 스마트 창, 조경익
초록
We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top-gate In-Ga-Znoxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si3N 4 and Al2O3, the electrical properties are analyzed. After post-annealing at 200°C for 1 hour in an O2 ambient, the sub-threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative-bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si-based broken bonds and hydrogenbased bonds. From constant-current stress tests of Id = 3 μA, an IGZO-TFT with heat-treated Si3N4 IDL shows a good stability performance, which is attributed to the compensation effect of the original charge-injection and electron-trapping behavior. Copyright © 2009 ETRI.
키워드
Electrical stability, IGZO, Interfacial dielectric layer, Thin-film transistor
KSP 제안 키워드
Atomic ratio, Bias stress, Constant current(CC), Dielectric materials, Electrical stability, Ga-Zn, Heat-treated, Interfacial trap, Low temperature(LT), Post-annealing, Si-based