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학술지 A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector
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저자
최광천, 이승우, 이범철, 최우영
발행일
201203
출처
IEEE Transactions on Circuits and Systems II : Express Briefs, v.59 no.3, pp.143-147
ISSN
1549-7747
출판사
IEEE
DOI
https://dx.doi.org/10.1109/TCSII.2012.2184370
협약과제
11MI1600, Scalable 마이크로 플로우 처리기술개발, 이범철
초록
A new type of sampling error corrector for a time-to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requiring additional counters or reclocking circuits. A TDC having the corrector is implemented in 90-nm CMOS logic technology. It has 13.6-ps/least significant bit resolution and 13-bit input dynamic range. It consumes 18 mW from a 1.2-V supply and occupies a 100 × 210 μm 2 chip area. © 2006 IEEE.
키워드
Counter, multiphase clock, sampling error correction, time-to-digital converter (TDC)
KSP 제안 키워드
90-nm, CMOS logic, Chip area, Error Correction, Least Significant Bit(LSB), Reference clock, Sampling error, Time-to-Digital Converter, binary counter, dynamic range, logic technology