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학술지 Pre-Silicidation Annealing Effect on Platinum-Silicided Schottky Barrier MOSFETs
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저자
전명심, 최철종, 최성진, 박영삼, 현영훈, 정태형, 장문규
발행일
201112
출처
Semiconductor Science and Technology, v.26 no.12, pp.1-4
ISSN
0268-1242
출판사
Institute of Physics (IOP)
DOI
https://dx.doi.org/10.1088/0268-1242/26/12/125004
협약과제
11ZE1100, ETRI 연구역량 강화를 위한 R&D체계 구축 및 Seed형 기술개발을 위한 창의형 연구 사업, 지경용
초록
We fabricated platinum-silicided p-type Schottky barrier MOSFETs (SB-MOSFETs) with 40 nm gate length on a silicon-on-insulator wafer. In order to improve the device performance, the devices were annealed at a temperature of 900 °C in a nitrogen environment prior to the platinum deposition for source/drain silicide formation. As a result, lowered threshold voltage of 1.2 V, subthreshold swing values of 110 mV and an enhanced on/off current ratio larger than 107 were obtained. This improvement is attributed to the reduction of the fixed oxide charge in the gate oxide during the annealing process. © 2011 IOP Publishing Ltd.
KSP 제안 키워드
40 nm, Annealing effects, Gate oxide, ON/OFF current ratio, Platinum deposition, Schottky barriers(SBs), Silicide formation, Silicon On Insulator(SOI), annealing process, device performance, gate length