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학술지 Design of a Clockless MSP430 Core using Mixed Asynchronous Design Flow
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저자
신지호, 오명훈, 이정근, 김학영, 김영우
발행일
201703
출처
IEICE Electronics Express, v.14 no.8, pp.1-12
ISSN
1349-2543
출판사
일본, 전자정보통신학회 (IEICE)
DOI
https://dx.doi.org/10.1587/elex.14.20170162
협약과제
17HS4100, 클라우드 인프라를 위한 초절전형 고집적 마이크로 서버 시스템 기술개발, 김학영
초록
There are various limitations on the supporting tools and design methodologies for the implementation of an asynchronous delay-insensitive model. In this paper, we propose a new design flow by exploiting a mixed model, which combines a bounded delay model and a delay-insensitive model. To develop the design flow, we use an asynchronous finite-state machine for the bounded delay model and the null convention logic for the delay-insensitive model. Further, we designed an MSP430 core to verify the proposed design flow and the results of simulation show that it exhibits a performance improvement of 30.34% over its synchronous counterpart.
키워드
AFSM, Asynchronous circuit, Bounded delay, Delay insensitive, NCL, UNCLE
KSP 제안 키워드
Asynchronous circuits, Bounded delay, Delay model, Delay-insensitive, Design flow, Mixed model, Supporting tools, asynchronous design, design methodology, finite state machine, null convention logic