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학술지 A 128-channel FPGA based Real-time Spike-sorting Bidirectional Closed-loop Neural Interface System
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저자
박종길, 김국화, 정상돈
발행일
201712
출처
IEEE Transactions on Neural Systems and Rehabilitation Engineering, v.25 no.12, pp.2227-2238
ISSN
1534-4320
출판사
IEEE
DOI
https://dx.doi.org/10.1109/TNSRE.2017.2697415
협약과제
16ZH1200, 실시간 뉴런-컴퓨터 양방향 통신 및 생체모방 시냅스 기술, 정상돈
초록
A multichannel neural interface system is an important tool for various types of neuroscientific studies. For the electrical interface with a biological system, high-precision high-speed data recording and various types of stimulation capability are required. In addition, real-time signal processing is an important feature in the implementation of a real-time closed-loop system without unwanted substantial delay for feedback stimulation. Online spike sorting, the process of assigning neural spikes to an identified group of neurons or clusters, is a necessary step to make a closed-loop path in real time, but massive memory-space requirements commonly limit hardware implementations. Here, we present a 128-channel field-programmable gate array (FPGA)-based real-time closed-loop bidirectional neural interface system. The system supports 128 channels for simultaneous signal recording and eight selectable channels for stimulation. A modular 64-channel analog front-end (AFE) provides scalability and a parameterized specification of the AFE supports the recording of various electrophysiological signal types with 1.59 짹 0.76 쨉V root-mean-square noise. The stimulator supports both voltage-controlled and current-controlled arbitrarily shaped waveforms with the programmable amplitude and duration of pulse. An empirical algorithm for online real-time spike sorting is implemented in an FPGA. The spike-sorting is performed by template matching, and templates are created by an online real-time unsupervised learning process. A memory saving technique, called dynamic cache organizing, is proposed to reduce the memory requirement down to 6 kbit per channel and modular implementation improves the scalability for further extensions.
키워드
Dynamic cache, Microelectrode array, Multichannel, Template matching.
KSP 제안 키워드
Analog Front-end, Arbitrarily shaped, Biological systems, Closed-Loop System, Data recording, Dynamic Cache, Electrical interface, Electrophysiological signal, Field Programmable Gate Arrays(FPGA), Hardware Implementation, High Speed