BROWSE
Detail
Journal Article
A 128-Channel FPGA-Based Real-Time Spike-Sorting Bidirectional Closed-Loop Neural Interface System
Cited 38 time in 
Share 
Share
- Authors
- Jongkil Park, Gookhwa Kim, Sang-Don Jung
- Issue Date
- 2017-12
- Citation
- IEEE Transactions on Neural Systems and Rehabilitation Engineering, v.25, no.12, pp.2227-2238
- ISSN
- 1534-4320
- Publisher
- IEEE
- Language
- English
- Type
- Journal Article
- Abstract
- A multichannel neural interface system is an important tool for various types of neuroscientific studies. For the electrical interface with a biological system, high-precision high-speed data recording and various types of stimulation capability are required. In addition, real-time signal processing is an important feature in the implementation of a real-time closed-loop system without unwanted substantial delay for feedback stimulation. Online spike sorting, the process of assigning neural spikes to an identified group of neurons or clusters, is a necessary step to make a closed-loop path in real time, but massive memory-space requirements commonly limit hardware implementations. Here, we present a 128-channel field-programmable gate array (FPGA)-based real-time closed-loop bidirectional neural interface system. The system supports 128 channels for simultaneous signal recording and eight selectable channels for stimulation. A modular 64-channel analog front-end (AFE) provides scalability and a parameterized specification of the AFE supports the recording of various electrophysiological signal types with 1.59 짹 0.76 쨉V root-mean-square noise. The stimulator supports both voltage-controlled and current-controlled arbitrarily shaped waveforms with the programmable amplitude and duration of pulse. An empirical algorithm for online real-time spike sorting is implemented in an FPGA. The spike-sorting is performed by template matching, and templates are created by an online real-time unsupervised learning process. A memory saving technique, called dynamic cache organizing, is proposed to reduce the memory requirement down to 6 kbit per channel and modular implementation improves the scalability for further extensions.
- KSP Keywords
- Analog Front-end, Arbitrarily shaped, Biological systems, Closed-loop systems, Data recording, Dynamic Cache, Electrical interface, Electrophysiological signal, Field-Programmable Gate Array(FPGA), Hardware implementation, High Speed