상세정보
학술지
Ultra-low Rate Dry Etching Conditions for Fabricating Normally-off Field Effect Transistors on AlGaN/GaN Heterostructures
- 발행일
- 201802
- 출처
- Solid-State Electronics, v.140, pp.12-17
- ISSN
- 0038-1101
- 출판사
- Elsevier
- 협약과제
- 17HB2400, 고효율 GaN 기반 기지국/단말기용 핵심부품 및 모듈 개발, 임종원
- 초록
- Enhancement-mode transistors with uniform turn-on threshold voltage (Vth) can be achieved using low damage and low rate gate recess etching techniques. In this work, dry etching conditions for a AlGaN/GaN heterostructure with an ultra-low etching rate of 1.5 nm/min were demonstrated and we succeeded the possibility to achieve a low etch rate of an AlGaN/GaN heterostructure in a Cl2/BCl3 plasma using inductively coupled plasma (ICP). The etching development was successfully implemented in the achievement of a normally-off GaN/AlGaN based transistor. The optimal recess depth was determined after fabrication of various devices with different recess depth values and with various dry etching conditions and after examining the performances of fabricated devices various conditions, and determining the dependence of recess time. The optimized etching condition resulted in low damage and smooth morphology of the etched AlGaN/GaN surfaces. Fine control of the depth of the gate region recess was achieved for the AlGaN/GaN heterostructure without any etch-stop layer, and validated for the fabrication of field effect transistors (FETs) using conventional processes. The fabricated normally-off Al2O3/AlGaN/GaN MOSFETs delivered a high positive Vth of +5.64 V with a low off-state leakage current of ~10?닋7 A/mm and lower current collapse.
- 키워드
- AlGaN/GaN HEMT, Compound semiconductor, Dry etching, GaN-on-sapphire, Recessed gate, Ultra-low rate
- KSP 제안 키워드
- 5 nm, AlGaN/GaN HEMTs, AlGaN/GaN heterostructure, Etch rates, Etch-stop, Etching conditions, Field effect transistors(Substrate temperature), Fine control, Gate recess, Inductively-coupled plasma(ICP), Leakage current