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학술대회 K-means Clustering-specific Lightweight RISC-V processor
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저자
이우영, 박진아, 변창준, 최은진, 이재형, 이우주, 변경진, 한규승
발행일
202110
출처
International SoC Design Conference (ISOCC) 2021, pp.391-392
DOI
https://dx.doi.org/10.1109/ISOCC53507.2021.9613863
협약과제
21HS3700, 경량 RISC-V 기반 초저전력 인텔리전트 엣지 지능형반도체 기술 개발, 구본태
초록
While the demand for edge devices performing K-means clustering algorithm is expected to explode, this paper introduces a K-means clustering-specific processor for edge devices. The processor consists of hardware to accelerate the K-means algorithm and lightweight RISC-V core, and functional validation has been completed through RTL simulation and FPGA prototyping. The processor prototype demonstrates its excellence by performing the K-means algorithm about 56 times faster.
키워드
acclerator, K-means clustering, RISC-V processor
KSP 제안 키워드
Edge devices, FPGA Prototyping, K-Means clustering algorithm, K-means algorithm, RISC-V, RTL simulation