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A 9-bit 100-MS/s Flash-SAR ADC without Track-and-Hold Circuits
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- Authors
- Young-Kyun Cho, Jae-Ho Jung, Kwang Chun Lee
- Issue Date
- 2012-08
- Citation
- International Symposium on Wireless Communication Systems (ISWCS) 2012, pp.880-884
- Language
- English
- Type
- Conference Paper
- Abstract
- A 9-bit 100 MS/s flash-successive approximation register (SAR) analog-to-digital converter (ADC), which is suitable for wireless communication systems, is presented. To reduce the active area and power consumption, front-end track-and-hold circuits in the flash ADCs are substituted by dynamic ones. A variable delay loop for enhancing dynamic performances is also included in the ADC. The prototype was fabricated using a 45 nm complementary metal-oxide-semiconductor technology with an active area of 0.068 mm 2. The differential and integral nonlinearities of the ADC are less than 0.94 and 0.66 LSB, respectively. At a 1.0 V supply and 100 MS/s, the ADC achieves a peak signal-to-noise-distortion ratio and spurious-free dynamic range of 51.94 and 65.87 dB, respectively and consumes 6.1 mW with the internal reference buffer. © 2012 IEEE.
- KSP Keywords
- 5 nm, Active area, Analog-to-digital converters(ADCs), Complementary metal-oxide-semiconductor(CMOS), Distortion ratio, Dynamic performance, Front-End, Internal reference, Metal-oxide(MOX), Power Consumption, Semiconductor technology