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학술대회 A 9-bit 100-MS/s Flash-SAR ADC without Track-and-Hold Circuits
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저자
조영균, 정재호, 이광천
발행일
201208
출처
International Symposium on Wireless Communication Systems (ISWCS) 2012, pp.880-884
DOI
https://dx.doi.org/10.1109/ISWCS.2012.6328494
협약과제
12MI1300, 차세대 이동통신 기지국용 Class-S 전력증폭기 기술 연구, 정재호
초록
A 9-bit 100 MS/s flash-successive approximation register (SAR) analog-to-digital converter (ADC), which is suitable for wireless communication systems, is presented. To reduce the active area and power consumption, front-end track-and-hold circuits in the flash ADCs are substituted by dynamic ones. A variable delay loop for enhancing dynamic performances is also included in the ADC. The prototype was fabricated using a 45 nm complementary metal-oxide-semiconductor technology with an active area of 0.068 mm 2. The differential and integral nonlinearities of the ADC are less than 0.94 and 0.66 LSB, respectively. At a 1.0 V supply and 100 MS/s, the ADC achieves a peak signal-to-noise-distortion ratio and spurious-free dynamic range of 51.94 and 65.87 dB, respectively and consumes 6.1 mW with the internal reference buffer. © 2012 IEEE.
키워드
asynchronous clock, dynamic comparator, flash ADC, Successive approximation register (SAR) analog-to-digital converter (ADC), track-and-hold
KSP 제안 키워드
5 nm, Active area, Analog to digital converter(ADC), Asynchronous clock, Complementary metal-oxide-semiconductor(CMOS), Distortion ratio, Dynamic Comparator, Dynamic performance, Front-End, Internal reference, Metal-oxide(MOX)