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Conference Paper
A Low Complexity Parallel Architecture of Turbo Decoder Based on QPP Interleaver for 3GPP-LTE/LTE-A
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- Authors
- Suchang Chae
- Issue Date
- 2012-12
- Citation
- IP-Embedded System Conference & Exhibition (IP-SOC) 2012, pp.1-5
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper propose an improved method called the modified warm-up-free parallel window (PW) MAP decoding schemes to implement highly-parallel Turbo decoder architecture based on the QPP (Quadratic Polynomial Permutation) interleaver of 3GPP LTE/LTE-A standards. In general, Turbo decoder needs long decoding time because of iterative decoding. To communicate with high speed, we have to shorten decoding time and it is possible by using QPP interleaver-based Turbo code of 3GPP LTE/LTE-A standards. Basically, the QPP interleaver has been giving attention since it provides contention-free interleaving functionality for highly-parallel Turbo decoders. So we have to have relatively short decoding time and reduced complexity of MAP decoder of Turbo codes. As a result, we have got the modified warm-up-free PW of 64 according to the maximum code block length, 6144 and we propose the improved Turbo decoder architecture with modified warm-up-free PW MAP decoding occupying one of the FSMC, BSMC, LLRC, (de-)interlever logic and its memory size of only PF·PW/4 respectively (where, PF means parallel factor). And we would like to improve the BER performances of modified warm-up-free PW MAP decoder compared with warm-up or slide window MAP decoding schemes. In order to improve BER performances of warm-up-free PW MAP Decoder, we initialize FSM, BSM and LLR computed in the previous iteration of the adjacent PW block. Therefore, we have got such the BER performance as that of warm-up or slide window MAP decoding schemes. And also, we have achieved the goal of PW MAP decoding for turbo decoder which has low complexity highly-parallel and high-speed architecture, and no degradation of BER performances.
- KSP Keywords
- 3GPP LTE/LTE-A, BER performance, Decoding time, High Speed, Highly parallel, Improved method, Long Term Evolution - Advanced(LTE-A), Low complexity, MAP decoding, Memory size, Parallel Architecture